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RF3133
0
Typical Applications * 3V Quad-Band GSM Handsets * Commercial and Consumer Systems * Portable Battery-Powered Equipment Product Description
The RF3133 is a high-power, high-efficiency power amplifier module with integrated power control. The device is self-contained with 50 input and output terminals. The power control function is also incorporated, eliminating the need for directional couplers, detector diodes, power control ASICs and other power control circuitry; this allows the module to be driven directly from the DAC output. The device is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 824MHz to 849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz, and 1850MHz to 1910MHz bands. On-board power control provides over 37dB of control range with an analog voltage input; and, power down with a logic "low" for standby operation. Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT
1.10 TYP 1.70 TYP 2.50 TYP 3.10 TYP 3.90 TYP 4.60 TYP 5.40 TYP 6.10 TYP 0.10 TYP 6.90 TYP 1 8.40 TYP 7.60 TYP 6.00 5.40 TYP 4.60 TYP 4.00 2.40 TYP 1.60 TYP
QUAD-BAND GSM850/GSM/DCS/PCS POWER AMP MODULE
* GSM850, EGSM900, DCS/PCS Products * GPRS Class 12 Compatible
1.40 1.25 1
9.90 TYP 9.10 TYP 8.50 6.90 TYP 6.10 TYP 3.90 TYP 3.10 TYP 1.50 0.90 TYP 0.10 TYP 0.00
10.00 0.10
7.00 0.10
NOTES:
0.450 0.075
1
Shaded areas represent pin 1 location.
!
Package Style: Module
GaAs HBT SiGe HBT GaN HEMT
!Si CMOS
GaAs MESFET
Features * Complete Power Control Solution * Single 2.9V to 5.5V Supply Voltage * +35dBm GSM Output Power at 3.5V * +33dBm DCS/PCS Output Power at 3.5V * 55% GSM and 52% DCS/PCS EFF
SiGe Bi-CMOS
12 DCS IN 1 BAND SELECT 2 TX ENABLE 3 VBATT 4 VREG 5 VRAMP 6 GSM IN 7 8 9 GSM OUT 10 VCC OUT 11 DCS OUT
VCC2
Ordering Information
RF3133 RF3133 PCBA VCC2 Quad-Band GSM850/GSM/DCS/PCS Power Amp Module Fully Assembled Evaluation Board
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Rev A4 030527
5.50 6.30 TYP 6.70 TYP
0.00
3.00
2-459
RF3133
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Input RF Power Max Duty Cycle Output Load VSWR Operating Temperature Storage Temperature
Rating
-0.3 to +6.0 -0.3 to +1.8 +11.5 50.0 10:1 -20 to +85 -55 to +150
Unit
VDC V dBm % C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Power Control VRAMP
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off Time
Specification Min. Typ. Max.
1.5 0.25 20 10 2
Unit
V V dB pF A S V V V V A V mA A V V A V V A
Condition
Max. POUT, Voltage supplied to the input Min. POUT, Voltage supplied to the input VRAMP =0.2V to VRAMP MAX DC to 2MHz VRAMP =VRAMP MAX VRAMP =0V to VRAMP MAX Specifications Nominal operating limits 50% duty cycle, Pulse width=2308s 50% duty cycle, 824MHz to 915MHz 50% duty cycle, 1710MHz to 1910MHz PIN <-30dBm, TXEnable=Low, Temp=-20C to +85C
0.2 35 15
Overall Power Supply
Power Supply Voltage 3.0 3.0 0.2 0.2 1 2.7 2.8 7 3.5 5.5 4.3 1.33 1.28 10 2.9 8 10 0.5 3.0 50 0.5 3.0 2
VRAMP Power Supply Current VREG Voltage VREG Current
TX Enable=High TX Enable=Low
Overall Control Signals
Band Select "Low" 0 Band Select "High" 1.3 Band Select "High" Current TX Enable "Low" 0 TX Enable "High" 1.3 TX Enable "High" Current Note: VRAMP Max=3/8*VBATT +0.18<1.5V 0 2.0 20 0 2.0 1
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Parameter Specification Min. Typ. Max. Unit Condition
Temp=+25 C, VBATT =3.5V, PIN =+2dBm, VREG =2.8V, VRAMP =VRAMP MAX, Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s +33.8 +31.5 Total Current Total Efficiency Input Power Range Output Noise Power 824 to 849 +35.0 +32.5 1.3 50 +2 -86 -87 Forward Isolation 1 Forward Isolation 2 Cross Band Isolation at 2fO Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness MHz dBm dBm A % dBm dBm dBm dBm dBm dBm dBm dBm dBm 2.5:1 8:1 10:1 VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz, Set VRAMP where POUT <34.0dBm into 50 load Set VRAMP where POUT <34.0dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad Temp = 25C, VBATT =3.5V, VRAMP =VRAMP MAX Temp=+85 C, VBATT =3.0V, VRAMP =VRAMP MAX POUT =+31dBm At POUT MAX, VBATT =3.5V Full output power guaranteed at minimum drive level RBW=100kHz, 869MHz to 879MHz, POUT > +5dBm RBW=100kHz, 879MHz to 894MHz, POUT > +5dBm TXEnable=Low, 0V, PIN =+5dBm TXEnable=High, PIN =+5dBm, VRAMP =0.2V VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX
Overall (GSM850 Mode)
Operating Frequency Range Maximum Output Power
40 0
+5 -82 -83 -30 -2 -13 -5 -15 -36
-18 -18 -28
50
Output Load Impedance Note: VRAMP Max=3/8*VBATT +0.18<1.5V
50
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Parameter Specification Min. Typ. Max. Unit Condition
Temp=+25 C, VBATT =3.5V, VRAMP Max, PIN =+2dBm, VRAMP =VRAMP Max, VREG =2.8V, Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s +34.2 +32.0 Total Efficiency Input Power Range Output Noise Power 47 0 880 to 915 +35.0 +32.8 53 +2 -86 -88 MHz dBm dBm % dBm dBm dBm dBm dBm dBm dBm Temp = 25C, VBATT =3.5V, VRAMP =VRAMP Max Temp=+85 C, VBATT =3.0V, VRAMP =VRAMP Max At POUT,MAX, VBATT =3.5V RBW=100kHz, 925MHz to 935MHz, POUT > +5dBm RBW=100kHz, 935MHz to 960MHz, POUT > +5dBm RBW=100kHz, 1805MHz to 1880MHz and 1930MHz to 1990MHz, POUT >0dBm f=925MHz to 960MHz, RBW=VBW=100kHz TX_ENABLE=0V, PIN =+5dBm TX_ENABLE=High, PIN =+5dBm, VRAMP =0.2V VRAMP =0.2V to VRAMPMax VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz, Set VRAMP where POUT <34.2dBm into 50 load Set VRAMP where POUT <34.2dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pad
Overall (EGSM900 Mode)
Operating Frequency Range Maximum Output Power
+5 -74 -82 -80 -73
Forward Isolation 1 Forward Isolation 2 Crossband Isolation at 2f0 Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness
-35
-30 -2 -20 -5 -15 -36 2.5:1
-28 -10 -21 50 8:1 10:1
dBm dBm dBm
Output Load Impedance Note: VRAMP Max=3/8*VBATT +0.18<1.5V
50
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Parameter Specification Min. Typ. Max. Unit Condition
Temp=25C, VBATT =3.5V, PIN =+2dBm, VREG =2.8V, VRAMP =VRAMP Max, Freq=1710MHz to 1910MHz, 25% Duty Cycle, Pulse Width=1154s +32.0 +31.7 +31.0 +29.5 45 44 0 1710 to 1910 +34.0 +32.7 +31.8 +30.5 50 48 +2 MHz dBm dBm dBm dBm % +5 -77 dBm dBm Temp=+25C, VBATT =3.5V, VRAMP =VRAMP Max, 1710MHz to 1785MHz 1850MHz to 1910MHz Temp=+85C, VBATT =3.0V, VRAMP = VRAMP Max, 1710MHz to 1785MHz 1850MHz to 1910MHz At POUT,MAX, VBATT =3.5V, 1710-1785MHz 1850MHz to 1910MHz RBW=100kHz, 1805MHz to 1880MHz and 1930MHz to 1990MHz, POUT > 5dBm, VBATT =3.5V TX_ENABLE=0V, PIN =+5dBm TX_ENABLE=High, PIN =+5dBm, VRAMP =0.2V VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX VRAMP =0.2V to VRAMP MAX Spurious<-36dBm, RBW=3MHz, Set VRAMP where POUT <32.0dBm into 50 load Set VRAMP where POUT <32.0dBm into 50 load. No damage or permanent degradation to part. Load impedance presented at RF OUT pin
Overall (DCS/PCS Mode)
Operating Frequency Range Maximum Output Power
Total Efficiency Input Power Range Output Noise Power
Forward Isolation 1 Forward Isolation 2 Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness
-37
-30 -1 -5 -15 -36 2.5
dBm dBm dBm dBm dBm
-25 -30 50 8:1 10:1
Output Load Impedance Note: VRAMP Max=3/8*VBATT +0.18<1.5V
50
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Pin 1 2 3 4 5 6 7 8 9 10 Function Description Interface Schematic DCS/PCS IN RF input to the DCS band. This is a 50 input. Allows external control to select the GSM or DCS band with a logic high BAND or low. A logic low enables the GSM band whereas a logic high enables SELECT the DCS band. TX ENABLE VBATT VREG VRAMP GSM IN VCC2 GSM OUT VCC OUT
This signal enables the PA module for operation with a logic high. Once TX Enable is asserted the RF output level will increase to -2dBm. Power supply for the module. This should be connected to the battery. Regulated voltage input for power control function. (2.8V nom) Ramping signal from DAC. A simple RC filter may need to be connected between the DAC output and the VRAMP input depending on the baseband selected. RF input to the GSM band. This is a 50 input. Controlled voltage input to driver stage for GSM bands. This voltage is part of the power control function for the module. This node must be connected to VCC out. RF output for the GSM band. This is a 50 output. The output load line matching is contained internal to the package. Controlled voltage output to feed VCC2. This voltage is part of the power control function for the module. It can not be connected to anything other than VCC2, nor can any component be placed on this node (i.e., decoupling capacitor). RF output for the DCS band. This is a 50 output. The output load line matching is contained internal to the package. Controlled voltage input to DCS driver stage. This voltage is part of the power control function for the module. This node must be connected to VCC out.
11 12 Pkg Base
DCS/PCS OUT VCC2 GND
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Pin Out
VCC2 PIN #1
DCS/PCS IN
DCS/PCS OUT
BAND SELECT
TX EN
VBATT
VCC OUT
10.00
VREG
VRAMP
GSM IN VCC2
GSM OUT
7.00
Rev A4 030527
2-465
RF3133
Application Schematic
2.2 nF
50 strip DCS/PCS IN BAND SELECT TX ENABLE VBATT VREG 15 k** VRAMP GSM IN 50 strip 6 7 1 2 3 4 5
12 11
50 strip DCS/PCS OUT
10
50 strip 9 8 GSM OUT
** Used to filter noise and spurious from baseband.
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
P1 1 GND CON1 P2-1 P2 1 VCC CON1 2.2 nF 50 strip DCS/PCS IN 1 BAND SELECT TX ENABLE VBATT 3.3 F* 2 3 4 VREG 5 6 15 k** VRAMP 50 strip GSM IN 7 8 9 50 strip GSM OUT 10 12 11 50 strip DCS/PCS OUT
1 nF*
*Not required in most applications. ** Used to filter noise and spurious from baseband.
2-466
Rev A4 030527
RF3133
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-Layer
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RF3133
Theory of Operation
Overview The RF3133 is a quad-band GSM/DCS/PCS power amplifier module that incorporates an indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop is fully self contained and required does not require loop optimization. It can be driven directly from the DAC output in the baseband circuit. Theory of Operation The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3133 does not use a power detector. A high-speed control loop is incorporated to regulate the collector voltages of the amplifier while the stages are held at a constant bias. The VRAMP signal is multiplied and the collector voltages are regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT TX ENABLE VRAMP
H(s)
RF IN TX ENABLE
RF OUT
By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3133 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
P dBm
( 2 V CC - V SAT ) = 10 log -------------------------------------------3 8 R LOAD 10
2
(Eq. 1)
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are: * * * * * * * * * * * Effective efficiency (eff) Current draw and system efficiency Power variation due to Supply Voltage Power variation due to frequency Power variation due to temperature Input impedance variation Noise power Loop stability Loop bandwidth variations across power levels Burst timing and transient spectrum trade offs Harmonics
2-468
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RF3133
Talk time and power management are key concerns in transmitter design since the power amplifier has the highest current draw in a mobile terminal. Considering only the power amplifier's efficiency does not provide a true picture for the total system efficiency. It is important to consider effective efficiency which is represented by EFF. (EFF considers the loss between the PA and antenna and is a more accurate measurement to determine how much current will be drawn in the application). EFF is defined by the following relationship (Equation 2):
m
PN - PIN
-------------------------------- 100 EFF = n = 1 P DC
(Eq. 2) Where PN is the sum of all positive and negative RF power, PIN the input power and PDC is the delivered DC power. In dB the formula becomes (Equation 3):
10 - 10 EFF = -----------------------------------------------V BAT I BAT 10
P PA + P LOSS ----------------------------10
P IN ------10
(Eq. 3)
Where PPA is the output power from the PA, PLOSS the insertion loss, PIN the input power to the PA and PDC the delivered DC power. The RF3133 improves the effective efficiency by minimizing the PLOSS term in the equation. A directional coupler may introduce 0.4dB to 0.5dB loss to the transit path. To demonstrate the improvement in effective efficiency consider the following example: Conventional PA Solution:
P PA = +33 dBm P IN = +2 dBm P LOSS = -0.4 dB V BAT = 3.5 V IBAT = 1.1 A
RF3133 Solution:
EFF = 47.2%
P PA = +33 dBm P IN = +2 dBm P LOSS = 0 dB V BAT = 3.5 V IBAT = 1.1 A
The RF3133 solution improves effective efficiency 5%.
EFF = 51.72%
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP.
Rev A4 030527
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RF3133
The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting the maximum VRAMP voltage (Equation 2). Although no compensation is required for typical battery conditions, the battery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to the terminal software.
3 V RAMP -- V BATT + 0.18 8
(Eq. 4)
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits the VRAMP voltage to correspond with the battery voltage. Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less. The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3133 does not use a directional coupler with a diode detector, these variations do not occur. Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO. The RF3133 presents a very constant load to the VCO. This is because all stages of the RF3133 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier. Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
F2 - 1 F3 - 1 F TOT = F1 + --------------- + ------------------G1 G1 G2
(Eq. 5)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3133 is kept constant the gain in the first stage is always high and the overall noise power is not increased when decreasing output power. Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions. The RF3133 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary. An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3133 is insensitive to a change in input power and the burst timing is constant and requires no software compensation.
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Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range or if the slope is simply to steep it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent. Harmonics are natural products of high efficiency power amplifier design. An ideal class "E" saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3133 address this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. Should a problem arise, these terminations should be explored. The RF3133 incorporates many circuits that had previously been required external to the power amplifier. The shaded area of the diagram below illustrates those components and the following table itemizes a comparison between the RF3133 Bill of Materials and a conventional solution:
Component Power Control ASIC Directional Coupler Buffer Attenuator Various Passives Mounting Yield (other than PA) Total Conventional Solution $0.80 $0.20 $0.05 $0.05 $0.05 $0.12 $1.27 RF3133 N/A N/A N/A N/A N/A N/A $0.00
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits VRAMP to correspond with the battery voltage.
Traditional Triple-Band PA
From DAC
*Shaded area eliminated with Indirect Closed Loop using RFMD's Integrated Power Control Solution
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PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD's qualification process is Electroless Nickel, immersion Gold. Typical thickness is 3inch to 8inch Gold over 180inch Nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land and Solder Mask Pattern
A = 0.80 (mm) Sq. Typ. B = 1.00 x 0.80 (mm) Typ. Pin 1 9.00 (mm) Typ. 8.30 (mm) 7.50 (mm) 6.00 (mm) 4.50 (mm) Typ. 3.00 (mm) 1.50 (mm) 0.70 (mm) 0.00 A A A 5.30 (mm) A A A 0.80 (mm) A A B 5.00 (mm) Typ. 5.90 (mm) Typ. 0.00 B 3.70 (mm) 3.00 (mm) Typ. 1.50 (mm) Typ. A A A 0.00 A B C C B E E D 0.05 (mm) Typ. 4.50 (mm) Typ. A B 8.20 (mm) 7.50 (mm) Typ. 6.00 (mm) Typ. A A A F C C C E E D 4.50 (mm) 9.00 (mm) Typ. A = 1.00 (mm) Sq. Typ. B = 0.90 x 0.80 (mm) Typ. C = 0.80 (mm) Sq. Typ. Pin 1 A A B B D D = 1.00 x 1.20 (mm) Typ. E = 0.80 x 1.10 (mm) Typ. F = 7.00 x 2.50 (mm) Typ. 9.05 (mm) Typ.
0.00 0.70 (mm) 1.50 (mm) 2.20 (mm) Typ.
1.50 (mm) 2.25 (mm) 3.00 (mm)
Metal Land Pattern
Solder Mask Pattern
Figure 1. PCB Metal Land and Solder Mask Pattern (Top View)
2-472
4.40 (mm) Typ.
5.90 (mm)
Rev A4 030527
RF3133
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The Via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Vias 0.203 mm to 0.330 mm Finished Hole 0.5 mm to 1.2 mm Grid
Figure 2. Thermal Pad and Via Design (RFMD Qualification)
Stencil Design Recommendation
The stencil aperture are typically designed to match the pad size shown in the PCB Solder Mask pattern and are reduced for an overall 20 percent reduction in pad area for each pad. This has yielded good solder joint results based on volumes assembled during product introduction phase. Critical parameters to consider for successful solder paste application include: Accurate registration of the stencil to the PCB during printing. Good release of stencil from the PCB after paste applied. This is improved with laser cut trapezoidal openings. Proper storage and handling of solder paste based on solder paste vendor guidelines. Frequent cleaning of the solder paste stencil to remove residual solder paste. Stencil material recommendations: 5mil (0.127mm) thick stainless steel, laser cut stencils with trapezoidal openings to promote easy release of solder paste.
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A = 0.64 (mm) Sq. Typ. B = 0.72 x 0.64 (mm) Typ. C = 0.64 x 0.80 (mm) Typ.
Pin 1
D = 0.64 x 0.88 (mm) Typ. E = 2.42 x 2.00 (mm) Typ. B B A E A A E A A C D D C D D C 0.05 (mm) Typ. 2.91 (mm) 6.09 (mm) 9.05 (mm) Typ.
9.00 (mm) Typ. 7.50 (mm) Typ. 6.00 (mm) Typ. 4.50 (mm) Typ. 3.00 (mm) Typ. 1.50 (mm) Typ. 0.00
A A A A A A A
A
A
B
B
1.50 (mm) Typ.
3.00 (mm) Typ.
4.40 (mm) Typ.
Figure 3. Stencil Recommendation
2-474
5.90 (mm) Typ.
0.00
2.25 (mm)
Rev A4 030527

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